The present invention relates generally to semiconductor devices, and, more particularly, to CMOS devices having transistors with mutually different punch-through voltage characteristics less susceptible to punch-through, and a method for manufacturing the same.
A CMOS device is generally-produced by forming PMOS and NMOS transistors in a semiconductor substrate, and electrically connecting them. Conventionally, after forming an N-well and P-well in the substrate, transistors having opposite conductivities are formed simultaneously in the wells and in the substrate between the wells, to thereby complete the CMOS device.
FIG. 1 depicts a CMOS device manufactured by a conventional method, the CMOS device including a P-type semiconductor substrate 10, an N-well 18, a P-well 22, a field oxide layer 26, a gate oxide layer 28, and gate electrodes 30. The CMOS device depicted in FIG. 1 is formed by the steps of selectively doping opposite conductivity-type impurities in spaced-apart surface regions of the semiconductor substrate 10, to thereby form the N-well 18 and the P-well 22, respectively, forming the field oxide layer 26 in the conventional manner, forming the gate oxide layer 26 on the surface of the resultant structure, and forming the gate electrodes 30 on the gate oxide layer 28.
As semiconductor devices become more highly integrated, the unit size of the constituent devices thereof decreases, thus commensurately degrading the electrical characteristics of each constituent device. For example, in the case of a transistor, if the gap (channel) between the source and drain thereof is reduced, the incidence of punch-through due to contact between source and drain depletion regions thereof increases.
The lower the impurity concentration of the substrate, the more frequently punch-through occurs. The incidence of punch-through is particularly high in very small scale transistors, because a lower impurity concentration in the vicinity of the source and drain depletion regions and the substrate translates into larger source/drain depletion regions.
Significant research into a method for increasing the punch-through voltage of a transistor by increasing the impurity concentration in the vicinity of the source and drain depletion regions thereof has been actively carried out. In this connection, U.S. Pat. No. 4,354,307, entitled xe2x80x9cMethod for mass producing miniature field effect transistors in high density LSI/VLSI chipsxe2x80x9d, issued to Vinson et al., discloses a method for increasing the punch-through voltage rating of a transistor by selectively increasing the impurity concentration of the substrate. However, since the bulk concentrations of the wells and the substrate which crucially influence electrical characteristics of transistors respectively formed in the wells and the substrate are not selectively adjusted for each transistor, it is difficult to achieve the different electrical characteristics required for each transistor.
For example, if the transistor formed in the substrate requires a specific punch-through voltage and the transistor formed in the well requires a back-bias at a given operating voltage, the transistor formed in the substrate should have a high punch-through voltage, which is generally attained by increasing the bulk concentration of the depletion region thereof. Further, as suggested by the following equation (1), the transistor formed in the well should have a low gamma (xcex3) value, which represents the variation of threshold voltage due to back-biasing greater than 
xcex3=(2xcex5sxcex50qNa)xc2xd/Cox,xe2x80x83xe2x80x83(1)
where Cox is the capacitance of the gate oxide layer 28, xcex5s is the dielectric constant of the semiconductor substrate 10, xcex50 is the dielectric constant of a vacuum, q is the charge quantity, and Na is the number of impurities. As can be understood from the above equation (1), in order to lower the xcex3 value, the value of qNa (i.e., bulk concentration) must be lowered. That is, when the transistor formed in the substrate requires a particular punch-through voltage and the transistor formed in the well requires reduced back biasing at a given operating voltage, the bulk concentration in the well should be different from that in the substrate.
However, using the conventional technique in which the respective bulk concentrations are not independently adjusted, it is not possible to manufacture transistors having mutually desirable characteristics at the same time. Rather, in order to achieve the required independent adjustment of the bulk concentrations, separate mask processing steps must be performed, which increases the cost and complexity, and reduces the efficiency and reliability of the manufacturing process.
Based on the above, it can be appreciated that there presently exists a need in the art for a CMOS device, and a method for manufacturing the same, which overcomes the above-described drawbacks and shortcomings of the presently available technology.
It is an object of the present invention to provide a CMOS device having transistors with mutually different punch-through voltage characteristics, simultaneously formed in a well and a substrate, respectively.
It is another object of the present invention to provide a method for manufacturing such a CMOS device.
The present invention encompasses a CMOS device which includes first and second wells formed in respective first and second regions of a semiconductor substrate, first and second transistors formed in the respective first and second regions, a third transistor formed in a third region of the substrate outside of the first and second wells, a first impurity layer formed in the vicinity of the depletion region of at least one but not more than two of the first, second, and third regions, and, a second impurity layer deeper than the first impurity layer and formed in the region(s) of the substrate in which the first impurity layer is not formed. The first and second wells are preferably of opposite conductivity types, e.g., the first well is an N-well and the second well is a P-well.
In a first preferred embodiment of the CMOS device, the first impurity layer is formed in the third region only. In a second preferred embodiment of the CMOS device, the first impurity layer is formed in the first and second regions only. In a third preferred embodiment of the CMOS device, the first impurity layer is formed in the first and third regions only. In a fourth preferred embodiment of the CMOS device, the first impurity layer is formed in the second region only. In a fifth preferred embodiment of the CMOS device, the first impurity layer is formed in the second and third regions only. In a sixth preferred embodiment of the CMOS device, the first impurity layer is formed in the first region only.
In all six preferred embodiments, the CMOS device preferably further includes a third impurity layer formed in the channel region of each transistor for adjusting the threshold voltage thereof. The concentration of the first and second impurity layers is preferably lower than that of the third impurity layer and is preferably higher than that of the substrate and wells.
The present invention also encompasses a method for manufacturing a CMOS device, which includes the steps of forming a first insulating layer on a major surface of a semiconductor substrate, removing a first portion of the first insulating layer from a first portion of the major surface of the substrate, forming a second insulating layer on the first portion of the major surface of the substrate and forming a first well in a region of the substrate beneath the second insulating layer, removing either the first or second insulating layer, to thereby leave a remaining insulating layer, and, forming a first impurity layer in a first region of the substrate beneath the remaining insulating layer, and a second impurity layer in a second region of the substrate uncovered by the remaining insulating layer.
The step of forming a first and a second impurity layer is preferably carried out by doping impurities in the entire surface region of said substrate. The first impurity layer is preferably formed to a first depth in the vicinity of the depth of a depletion region of a transistor formed in the first region of said substrate. The method also preferably further includes the step of doping impurities to a depth less than the first depth, in the entire surface region of the resultant structure, to thereby form a third impurity layer.
The concentration of the first and second impurity layers is preferably lower than that of the third impurity layer, and is preferably higher than that of the substrate and first well. The first insulating layer is preferably formed to a thickness of 1,000-2,000 angstroms, the second insulating layer is preferably formed to a thickness of 4,000-6,000 angstroms, and the impurities are preferably doped at an energy level of 400-600 keV.
In a preferred embodiment, the method further includes, after the step of forming a second insulating layer, the steps of removing a second portion of the first insulating layer from a second portion of the major surface of the semiconductor substrate, forming a third insulating layer on the second portion of the major surface of the substrate, and then forming a second well in a second region of the substrate beneath the third insulating layer. The first and second wells are preferably of opposite conductivity types, e.g., the first well is an N-well and the second well is a P-well. The second well may be formed in the first well, or vice versa.
A significant feature of the present invention resides in the fact that the bulk concentration outside the depletion region of a transistor whose punch-through voltage is not desired to be adjusted does not affect the xcex3 value, since the impurities doped to form the first and second impurity layers are doped below the depletion region of the transistors whose punch-through voltage is not desired to be adjusted. In this manner, a first impurity layer is formed to the depth of the:depletion region of a transistor(s) requiring a high punch-through voltage, and a second impurity layer is formed to a depth greater than the depth of the depletion region of a transistor(s) which does not require a high punch-through voltage, so that the operating voltage thereof is not affected by back bias.